Integrated circuit memory devices are widely used in many commercial and consumer applications. One widely used integrated circuit memory device is a Dynamic Random Access Memory (DRAM). Synchronous DRAM (SDRAM) devices also have been designed, which are capable of reading and writing data in synchronism with the rising edge or falling edge of a clock signal. Moreover, Dual Data Rate (DDR) SDRAM devices also have been designed which can operate at a higher frequency than a conventional SDRAM (also referred to as a Single Data Rate (SDR) SDRAM) by reading and/or writing data in response to both the rising edge and the falling edge of a clock signal. It will be understood by those having skill in the art that as used herein, the term “data rate” means the number of bits transferred to or from an external input/output terminal by a memory device, in a clock cycle.
FIG. 1 is a timing diagram that compares operation of a conventional SDR SDRAM and a conventional DDR SDRAM. Both of these SDRAMs include a Burst Length (BL) of 4 and a Column Address Strobe (CAS) latency (CL) of 2. Thus, as shown in FIG. 1, for the SDRAM having BL=4 and CL=2, 4 bits of data Q0, Q1, Q2 and Q3 are read in response to a read command R where each bit of data Q0-Q3 is output in response to the rising edge of a clock CLK. Similarly, in response to a write command W, 4 bits of data are input sequentially in response to the rising edge of the clock CLK.
In contrast, as also shown in FIG. 1, for a DDR SDRAM, stored data Q0-Q3 is output from the memory device in response to both the rising edge and the falling edge of a data strobe signal (DQS) which itself is generated from the clock signal CLK. Also, in response to a write command, data D0-D3 is written into the memory device in response to both the rising and falling edges of DQS, so that a double data rate is obtained compared to the SDR SDRAM. The design and operation of SDRAM devices, including SDR SDRAM devices and DDR SDRAM devices, are well known to those having skill in the art and need not to be described further herein.
Due to the high data rates, it may be difficult to test a high frequency memory device such as a DDR SDRAM. It also may be particularly difficult to test a high frequency memory device such as a DDR SDRAM using relatively low frequency test equipment, such as test equipment that is designed to test an SDR SDRAM. For example, U.S. Pat. No. 5,933,379 to Park et al, assigned to the assignee of the present application, provides a “Method and Circuit for Testing a Semiconductor Memory Device Operating at High Frequency”, as noted in the Park et al. title. As noted in the Park et al. Abstract, a circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency “n” times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.
U.S. Pat. No. 6,163,491 to Iwotomo et al. describes a “Synchronous Semiconductor Memory Device Which Can Be Inspected Even With Low Speed Tester” as noted in the Iwotomo et al. title. As noted in the Iwotomo et al. Abstract, a synchronous semiconductor memory device includes a prefetch selector receiving first and second data respectively read from first and second memory cells corresponding to even and odd addresses for outputting them to a data input/output terminal. The prefetch selector sequentially outputs first and second data to the data input/output terminal in one period of a clock period in the normal operation, determines if the first and second data match in a test mode, and outputs the determination result to the data input/output terminal in one period of the clock period.
Finally, U.S. Pat. No. 6,212,113 to Mader describes a “Semiconductor Memory Device Input Circuit” as noted in the Mader titled. As noted in the Mader Abstract, a double-data rate (DDR) memory device is disclosed that can be configured for testing on an ordinary memory tester. The DDR memory may include a DDR input circuit, a single data rate input circuit, a word line control circuit, a bit line control circuit, and a memory cell array. Normal write operations may be performed by selecting the DDR input circuit. Test write operations may be performed by selecting the SDR input circuit. Such an arrangement can enable a DDR memory device to be tested in an ordinary SDR memory tester
It may also be difficult to test a high frequency memory device such as a DDR SDRAM because the high frequency memory device may have a relatively small valid data window margin, which may be caused by process variations in the device fabrication line. Thus, even though a high frequency device such as a DDR SDRAM may be tested with high frequency test equipment for a DDR SDRAM, it may be difficult to actually test multiple DDR SDRAM devices in parallel.